The invention relates to hardware emulation.
As shown in FIG. 1, a computer system 8 may use a direct memory access (DMA) controller 14 to transfer data between peripheral devices (e.g., a sound card 28 and a floppy disk drive controller 34) and a system memory 12. This is typically done when the peripheral devices are connected to a bus (e.g., an Industry Standard Architecture (ISA) bus 17) which does not allow the peripheral devices to directly access the system memory 12. If not for the DMA controller 14, a central processing unit (CPU) 10 of the computer system 8 would directly oversee the transfer of data between the peripheral devices and the system memory 12, and all of the data would pass through registers of the CPU 10. However, with the DMA controller 14, the CPU 10 is not directly involved in the system memory 12 accesses, thereby freeing the CPU 10 to perform other functions.
To identify the peripheral device associated with the direct memory access, seven DMA channels 0-3 and 5-7 (channel 4 is unavailable) of the ISA bus 17 are typically used. As an example of the assignments for the DMA channels, the sound card 28 might be assigned to DMA channel 1, and the floppy disk drive controller 34 might be assigned to DMA channel 2. Because the computer system 8 is only capable of handling the transfer of data for one DMA channel at a time, the DMA controller 14 prioritizes and selectively grants requests for the DMA channels.
Each DMA channel has corresponding registers 20, 22 and 24 in the DMA controller 14. The CPU 10 uses the registers 20-24 to set up a pending data transfer for one of the DMA channels. The CPU 10 stores a base address in one of eight (one associated with each channel) base address registers 20. The base address is the address in system memory 12 where the first portion of the pending transfer is written or read. The CPU 10 stores a transfer count in one of eight (one associated with each channel) transfer count registers 22. The transfer count specifies the number of DMA cycles in the pending data transfer. The CPU 10 programs control registers 24 with the type (e.g., a read) and operational mode (e.g., a block transfer) of the pending data transfer.
Once a DMA channel is set up by the CPU 10, the CPU 10 may then issue a command directing a transaction to occur between a peripheral device associated with the DMA channel and the system memory 12. When the peripheral device responds to the command, the peripheral device submits a request to the DMA controller 14 to use the associated DMA channel. After the DMA controller 14 grants the request, the data transfer begins with the DMA controller 14 furnishing the addresses to the bus 17 and the peripheral device (and system memory 12) handling the data transactions on the bus 17.
As shown in FIG. 2, unlike the older computer systems 8, more recent computer systems 40 have buses (e.g., a Peripheral Component Interconnect (PCI) bus 44) which allow peripheral devices 45 (e.g., PCI bus devices) to directly access the system memory 12. Therefore, the peripheral devices 45 may transfer data to and from the system memory 12 without receiving aid from a CPU or a DMA controller.
To make the peripheral devices 45 compatible with older software driver routines (e.g., DOS-based software written to control specific hardware of the devices 45) which assume the peripheral devices 45 cannot directly access the system memory 12, the computer system 40 might have a distributed DMA (DDMA) or PC/PCI controller 43 built into a bridge circuit 42. The controller 43 emulates the functions of the DMA controller 14 for pseudo DMA channels assigned to (for the benefit of the older software driver routines) the peripheral devices 45. The DMA controller 14 remains in control of the DMA transfers for peripheral devices (e.g., the floppy disk drive controller 34) connected to the ISA bus 17; however, the controller 43 intercepts accesses which are associated with the pseudo DMA channels. After the access is intercepted, the controller 43 reads from or writes to (according to the type of access attempted) a set of peripheral device registers 47 that are associated with the pseudo DMA channel. The peripheral device 45 then performs transactions between the system memory 12 and the peripheral device 45 based on the information in the registers 47.
Instead of using the address/data lines of the PCI bus 44, sideband signals of the PCI bus 44 might be used to establish DMA communication between the controller 43 and the peripheral devices 45. This technique is used by the PC/PCI controller.